1. Field of the Invention
The present invention relates to processing of semiconductor wafers and other electronic substrates such as slices of semiconductor silicon and other articles requiring a planar surface and, more particularly, to a method and apparatus for planarizing a dielectric layer on a semiconductor wafer by removing an edge bead of the dielectric formed at the periphery of the semiconductor wafer during polishing of the wafer and/or forming a profiled dielectric layer which when planarized using, e.g., chemical mechanical polishing, forms a planar surface.
2. Description of Related Art
In the manufacture of integrated circuits, wafer surface planarity is of extreme importance. Photolithographic processes are typically pushed close to the limit of resolution and it is essential that the wafer surface be highly planar so that the electromagnetic or other radiation used to create the integrated circuit may be accurately focused in a single level thus resulting in precise imagining over the entire surface of the wafer. Wavy, curved or wedge-shaped semiconductor disks result in lack of definition when, for example, a photosensitive resist is applied to the surface of the disk and exposed.
One of the fabrication steps in the manufacture of integrated circuit devices is to apply a layer of dielectric to the wafer as a dielectric layer or interlayer. The dielectric layer is typically a glass such as SiO2 and doped glasses such as PSG, BSP, BPSG and the like. The dielectric layers are sometimes annealed to reflow the deposited dielectric and planarize the dielectric layer. Unfortunately, this procedure is not sufficient to produce ultra high density integrated circuits and additional steps are typically required to further planarize the surface.
Such a further processing step is the chemical-mechanical planarization process (CMP) which involves pressing a semiconductor wafer or other such electronic component or other substrate against a moving polishing surface that is wetted with a chemical reactive, abrasive slurry. The slurries are usually either basic or acidic and generally contain alumina, silica or other ceramic particles. The polishing surface is typically a planar pad made of a relatively soft, porous (open pored) material such as cast polyurethane. The pad is usually mounted on a rotatable planar platen.
In general, the wafer is secured to a carrier plate (or wafer carrier) by vacuum or by a mounting medium such as an adhesive, with the wafer having a forced load applied thereto through the carrier by a pressure plate so as to press the wafer into frictional contact with a polishing pad mounted on a rotating turntable. The carrier and pressure plate also rotate as a result of either the driving friction from the turn table or rotation drive means directly attached to the pressure plate.
An edge bead or a xe2x80x9clipxe2x80x9d of dielectric typically remains on the face of the wafer after CMP. The edge bead is generally a circumferential ring about 2 to 8 mm in width from the edge of the wafer. The edge bead or lip in general gradually increases in thickness toward the wafer edge to about 1000-3000 xc3x85 thicker than the dielectric in the central portion of the wafer. As noted above, a thicker dielectric area on portions of the wafer surface may lead to electrical problems such as open contacts and the like. The use of a reactive ion etch (RIE) is typically sufficient to open vias in normal thickness dielectric in the middle of the wafer, but if there is not enough over etch, the RIE will not reach the bottom of the thicker dielectric layer in the edge bead. The edge bead can also prevent focusing by lithography tools at the edge of the semiconductor wafer since the raised area will be out of focus with the lithography tool. Basically, elimination of the edge bead to provide a planar semiconductor surface increases the number of acceptable chips which can be made on each wafer.
Bearing in mind the problems and deficiencies of the prior. art, it is therefore an object of the present invention to provide a method to improve planarity of a dielectric layer on a semiconductor wafer and other such electronic component workpieces which have been planarized using a chemical mechanical planarization or other such process.
It is another object of the present invention to provide an apparatus for the chemical mechanical planarization of the dielectric layer on a semiconductor wafer or other electronic workpieces.
It is an additional object of the present invention to provide a method and apparatus for forming a profiled dielectric layer on a semiconductor wafer which when planarized using CMP or other such process forms a planar dielectric surface.
It is a further object of the present invention to provide flat planar workpieces, including semiconductor wafers, made using the improved method and apparatus of the invention.
Other objects and advantages of the present invention will be readily apparent from the following description.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed, in a first aspect, to a method for planarizing a dielectric layer on a semiconductor wafer or other workpiece comprising the steps of:
applying a resist to a dielectric coated wafer to coat the wafer with a layer of the resist;
removing the resist from a circumferential peripheral portion of the wafer from which the dielectric material is desired to be removed and leaving the resist on a central portion of the wafer;
exposing the partially resist coated wafer to a dry or wet etchant which etches the dielectric layer not covered by the resist;
etching the partially resist coated wafer for an effective etching time until the desired amount of dielectric material is removed from the circumferential peripheral portion forming a profiled dielectric layer having a thinner dielectric peripheral portion than the remaining central dielectric portion of the wafer;
removing the resist from the central portion of the etched wafer; and
planarizing the profiled dielectric layer by CMP or other polishing or planarization process.
In another aspect of the invention, the dielectric may be a glass such as SiO, PSG, BSG, BPSG and the like. In a preferred aspect, the dielectric layer is SiO2 and the etchant is a reactive ion etch or wet etch.
In an additional aspect of the invention, a method for planarizing a dielectric layer on a semiconductor wafer is provided comprising the steps of:
securing, to a rotatable turntable, preferably horizontal, a dielectric coated wafer;
rotating the turntable and the dielectric coated wafer;
applying a liquid etchant to a circumferential peripheral portion of the wafer preferably in the form of a spray to remove dielectric material from the circumferential peripheral portion of the wafer;
continuing the spraying until the desired amount of dielectric is removed providing a semiconductor wafer having a profiled dielectric layer wherein the dielectric peripheral portion is thinner than the remaining central dielectric portion of the wafer; and
planarizing the profiled dielectric layer by CMP or other polishing process.
In another aspect of the invention, the method comprises using a spray nozzle providing an etchant spray.
In an additional aspect of the invention, the liquid etchant is applied to the wafer by an apparatus comprising a rotating turntable, preferably horizontal, to rotate a wafer thereon and a distribution conduit preferably containing a spray nozzle which conduit moves back and forth over the area to be etched. It is preferred that the outlet of the distribution conduit be positioned less than about 0.5 inch above the surface of the wafer and preferably adjacent the surface. It is also preferred that the flow rate of the spray be about 1 to 100 ml/min.
In a further aspect of the invention, a semiconductor wafer to be planarized is first polished by a CMP process and then the resulting edge bead removed by etching or by further CMP of the wafer on only the edge bead portion of the wafer. These methods are not preferred with profiling of the dielectric layer (thinner peripheral dielectric edge) before CMP being preferred.
In an additional aspect of the invention, a method for planarization of a dielectric layer on a semiconductor wafer comprises the steps of:
planarizing the dielectric surface of the wafer by CMP wherein a polishing pad of the apparatus used for the CMP contacts the dielectric layer; and
planarizing the edge bead of the surface of the wafer by polishing the peripheral edge of the surface of the wafer by contacting the peripheral edge of the wafer with the polishing pad of a CMP apparatus so that the peripheral edge of the surface of the wafer contacts the polishing pad.
In a further aspect of the invention, a method for planarizing a dielectric layer on a semiconductor wafer comprises the steps of:
planarizing the dielectric surface of the wafer by CMP and forming a wafer having a peripheral edge bead; and
planarizing the peripheral edge of the face of the wafer using a rotating polishing pad having a diameter about the width or less than the width of the edge bead the polishing pad contacting the peripheral edge bead of the surface of the wafer.
It is another aspect of the invention to provide planar workpieces such as semiconductor wafers made using the improved method and apparatus of the invention.